As the semiconductor packaging technology advances, there have been developed many different types of semiconductor packages. In general, a semiconductor package is formed by mounting a semiconductor chip on a substrate or lead frame, electrically connecting the chip to the substrate or lead frame, and then encapsulating the chip and the substrate or lead frame via a resin material. One of the advanced semiconductor packages is referred to as ball grid array (BGA) package, which is characterized in using a circuit board with the chip being mounted on a front surface thereof, and implanting a plurality of array-arranged solder balls on a back surface of the circuit board via a self-alignment technique. This arrangement allows more solder balls serving as I/O connections to be accommodated on a unit area of the circuit board acting as a chip carrier, which is desirable for a highly integrated semiconductor chip, and the solder balls serving as I/O connections are used to electrically connect the package to an external printed circuit board.
In a conventional BGA package, the chip is directly attached to a top surface of the substrate and the solder balls are mounted on a bottom surface of the substrate. This vertical stacking or mounting manner increases the overall height of the BGA package, making it hard to reduce the size or height of the package. To achieve the purpose of reducing the package height, there is provided a hole formed in the substrate, allowing the chip to be received in the hole and thus flush with the substrate. Related prior arts include U.S. Pat. Nos. 6,515,356, 6,486,537, 6,586,824 and 5,646,316.
Referring to FIG. 3A showing a cavity down BGA (CDBGA) semiconductor package disclosed in U.S. Pat. No. 6,515,356, this package comprises a substrate 21 formed with a hole 211; a semiconductor chip 22 mounted in the hole 211 and electrically connected to the substrate 21 via bonding wires 23; an encapsulation body 24 for filling the hole 211 and encapsulating the chip 22 and bonding wires 23; and a plurality of solder balls 25 mounted on a bottom surface of the substrate 21.
As shown in FIG. 3B, during the process for mounting the chip 22 in the hole 211 of the substrate 21, since the hole 211 penetrates the substrate 21, the substrate 21 is turned upside down to make its bottom surface (where the solder balls 25 are mounted) face upwards, and it is required to attach a tape 26 to a top surface (now facing downwards) opposite to the bottom surface to seal an opening of the hole 211, such that the chip 22 can be placed in the hole 211 and attached to the tape 26. Subsequently, further referring to FIG. 3A, the bonding wires 23 are formed to electrically connect the chip 22 to the substrate 21, the encapsulation body 24 is molded, and the solder balls 25 are implanted on the bottom surface (facing upwards) of the substrate 21. Finally, the whole structure is turned over to make the tape 26 face upwards, and the tape 26 is then removed. This completes fabrication of the CDBGA package having the chip 22 received in the hole 211 of the substrate 21, with active surfaces of the substrate 21 and the chip 22 where the bonding wires 23 are formed both facing downwards.
Referring to FIGS. 4A to 4C, a cavity up ball grid array (CUBGA) semiconductor package disclosed in U.S. Pat. No. 6,586,824 has a structure substantially similar to that of the foregoing CDBGA package. As shown in FIGS. 4A to 4C, the only difference is that in the CUBGA package, active surfaces of a substrate 31 and a chip 32 where bonding wires 33 are formed face upwards, and an encapsulation body 34 is formed at the top of the package. In general, the CUBGA package is formed by forming a hole 311 in the substrate 31; placing the chip 32 in the hole 311 and electrically connecting the chip 32 to the top active surface of the substrate 31 via bonding wires 33; forming an encapsulation body 34 to encapsulate the chip 32 and bonding wires 33; and then mounting a plurality of solder balls 35 on a bottom surface of the substrate 31.
Similarly since the hole 311 penetrates the substrate 31, it is required to use a tape 36 to seal the bottom of the hole 311, and then the chip 32 can be placed in the hole 311 and attached to the tape 36. After the bonding wires 33 are formed to electrically connect the chip 32 to the substrate 31 and the encapsulation body 34 is molded, the tape 36 is removed and finally the plurality of solder balls 35 are implanted on the bottom surface of the substrate 31. This thus completes fabrication of the CUBGA package.
The CUBGA package differs from the CDBGA package in that, the active surface of the chip 32 for electrical connection with the bonding wires 33 faces upwards, but the solder balls 35 for external electrical connection are mounted on a surface of the substrate 31 facing downwards. Compared to the CDBGA package, one drawback of the CUBGA package is that the substrate 31 must be turned over twice to complete the electrical connection. The CDBGA package and CUBGA package are common in that, before mounting the chip 22, 32, the tape 26, 36 is required to seal the hole 211, 311 of the substrate 21, 31 so as to allow the chip 22, 32 to be subsequently placed in the hole 211, 311 and positioned by the tape 26, 36, and then the encapsulation body 24, 34 is formed to hold the chip 22, 32 in place in the hole 211, 311.
However, since the chip 22, 32 is positioned and held in place by means of the tape 26, 36 and the encapsulation body 24, 34, the package cannot be subject to other connection manners such as stacking of multiple chips or stacking of multiple substrates, thereby reducing the flexibility in application of the packaged product.
Moreover, when the encapsulation body 24, 34 is applied for filling the hole 211, 311 of the substrate 21, 31 so as to fix the chip 22, 32 in place, since the tape 26, 36 is directly attached to the chip 22, 32 and partially exposed in the hole 211, 311, the tape 26, 36 may also be adhesive to the encapsulation body 24, 34 especially when being molten, thereby making it very difficult to completely remove the tape 26, 36 from the substrate 21,31, or leaving residues of the tape 26, 36 on the substrate 21,31 due to incomplete removal of the tape 26, 36. As a result, the appearance of the package is deteriorated.
In addition, further as to the chip 22, 32 being temporarily positioned by the tape 26, 36 in the hole 211, 311, since the contact area between the chip 22, 32 and the tape 26, 36 is substantially small, the positioning strength provided for the chip 22, 32 from the tape 26, 36 is not very strong, such that during subsequent wire-bonding or encapsulating process, the chip 22, 32 may be shifted in place or dislocated. This problem should be addressed and solved.
Furthermore, for a wire-bonded package or a flip-chip package that is employed frequently for the chip package now, the substrate fabricating process and the chip packaging process require different machines and procedures, making the fabrication processes of the package very complicated and costly. In particular for the wire-bonded package, the bonding wires are arranged in very high density around the chip, which would easily lead to contact between adjacent wires and cause short circuit, thereby increasing the difficulty in performing the wire-bonding process. Moreover, during a molding process for forming the encapsulation body, the substrate mounted with the chip and bonding wires is placed in a cavity of an encapsulating mold, allowing an epoxy material to be injected into the mold cavity to form the encapsulation body and encapsulate the chip and bonding wires. However, in practice, due to the various designs of semiconductor packages, the size of the mold cavity and clamping positions do not always match any particular semiconductor structure to be packaged, which may cause a problem of insufficient clamping and in such a case, the epoxy material would easily flash to the surface of the substrate. This not only affects the planarity and appearance of the semiconductor package, but may also contaminate the area on the substrate where the solder balls are to be implanted. As a result, the quality of electrical connection as well as the yield and reliability of the semiconductor package are seriously degraded.
Typically the fabrication processes of a semiconductor device starts from preparation of a suitable chip carrier via a chip carrier manufacturer (such as substrate or circuit board manufacturer) for the semiconductor device. Then, the chip carrier is transferred to a semiconductor packaging manufacturer to undergo subsequent die-bonding, molding, and ball implanting processes, etc., so as to produce the semiconductor device having electronic functions required by a client. Therefore, the fabrication processes of the semiconductor device involve a number of different manufacturers, including the chip carrier manufacturer and the semiconductor packaging manufacturer, thereby making the fabrication processes complicated in practice and not easy to achieve interface integration. In case the client wishes to modify the product design, the changes and integration involved are even more complicated, not meeting the requirements of flexibility in change and economical benefit.